The present invention relates to a carrier recovery (CR) circuit, and more particularly to a CR circuit for offset quadrature phase shift keying (O-QPSK) modulators in which the preamble field of two sequences of burst signals, which undergo quadrature modulation by the O-QPSK system, is set in a prescribed bit pattern.
Both the O-QPSK system and the quadrature phase shift keying (QPSK) system are digital signal modulating systems having the common feature that two carriers of two series of binary digits, differing in phase from each other by 90.degree., undergo two-phase modulation to generate two modulated carriers in an orthogonal relationship to each other, and four-phase modulated carriers, resulting from the addition of the modulated carriers to the initial two carriers, are sent out to the transmission path, but there is the difference between them, as illustrated in FIG. 2, in the phase relationship between the two series of binary digits.
Thus, while the phase transition of binary digits (data) of two series on the in-phase channel (I-channel) and the quadrature channel (Q-channel) occur at the same time in the QPSK system as shown in FIG. 2 (A), those of data of two series on the I-channel and the Q-channel in the O-QPSK system arise in the middle of each other's data transmission periodic.
Since 180.degree. phase transition doesn't occur in the O-QPSK system as a result, there arises an effect to suppress the envelope fluctuations of modulated carriers, which means less susceptibility to non-linear distortions from a non-linear transmission path. Therefore, in a system having inevitable non-linear characteristics on the transmission path such as a satellite communication system, the O-QPSK system has an advantage over the QPSK system, and accordingly is used more frequently in satellite communication systems.
In a satellite communication system using Time Division Multiple Access (TDMA), signals are transmitted in the form of a succession of short-duration bursts. So that the burst signals can be efficiently demodulated in a short demodulator signal acquisition time, they have a bit structure that a preamble field 300 consisting of a Carrier Recovery field (CR field) 301 and an ensuing Bit Timing Recovery field (BTR field) 302 precedes a Unique Word (UW) 303 at the top of a data field 304 as shown in FIG. 3. In the CR field 301 and the BTR field 302, fixed bit patterns are set for the carrier recovery and bit timing recovery, respectively.
It is well known that, in a satellite communication system based on the O-QPSK system in which carrier recovery and clock recovery are closely related to each other, the CR field 301 and the BTR field 302 of the preamble field 300 of said burst signals should most desirably have such patterns as are illustrated in FIG. 4.
On the I-channel of the two orthogonal sequences in the O-QPSK system, both the signal for carrier recovery in the CR field 301 and that for bit timing recovery in the BTR field 302 wholly consist of binary 1's (or 0's ) as shown in FIG. 4 (A). However, on the Q-channel, that in the CR field 301 wholly consists of binary 1's (or 0's), while that in the BTR field 302 is an alternating series of binary 1's and 0's as shown in FIG. 4 (B).
When the O-QPSK modulated carriers differing in composition of the preamble field 300 between the two sequences of signals as described above are to be demodulated by synchronous detection, there arises the problem of how to configure the CR circuit. As the CR circuit in the QPSK system uses a Costas loop (phase locked loop), the use of this Costas loop is conceivable in the O-QPSK system as well.
However, in a satellite communication system, demodulation is accomplished under a low C/N ratio (the ratio of carrier power to noise power) condition and, moreover, the preamble field is minimized in length with a view to enhancing the utilization efficiency of signals. Thus, carrier recovery may not be completed within the duration of the CR field 301, leaving a phase error of the carrier at the beginning of the BTR field 302. Therefore, it is essential to enable carrier recovery to be carried over into the BTR field 302.
However, since it is usual that no clock synchronization is as yet achieved at the beginning of the BTR field 302, there is the problem that, even if a delay circuit is inserted into the Costas loop to make the phase between I-channel data and Q-channel data coincident, carrier recovery may become impossible in the BTR field 302 if the preamble field is composed as shown in FIG. 4.
Thus, if the carrier recovery is attempted with the BTR field 302 of the composition of FIG. 4 in a state where proper sample timing is not achieved, an error will arise in the estimated phase value obtained by a phase comparator in the Costas loop, and if a voltage controlled oscillator (VCO) is controlled by the output of loop filter contained the phase error, the CR circuit may become unlocked.
In view of this problem, when a CR circuit according to the prior art detects the arrival of the BTR field, a prescribed binary pattern (1010) instead of the output of a four-phase comparator is applied to the input of the loop filter for the duration of the BTR field.
FIG. 1 illustrates the configuration of this prior art CR circuit. In this diagram, reference numerals 11 and 12 denote multipliers; 13, a .pi./2 phase shifter; 15, a Voltage Controlled Oscillator (VCO); 50, a switch, 23, a loop filter; 16, a BTR field detector (BTR DET); and 21, a control circuit (CONT).
In this configuration, in the Costas loop for carrier recovery in the O-QPSK system, a 1/2 symbol delay circuit 14 for delaying by 1/2 symbol rate is inserted in order to coincide the phase transitions between the I and Q channels of burst signals entered into the two orthogonal channels, and at the same time the switch 50 is provided on the input of the loop filter 23, with the BTR field detector 16 and the control circuit 21 further being provided to control this switch 50.
This configuration enables the control circuit 21 to control the switch 50 so that the output of the four-phase comparator (4.phi. COMP) 20 will be made the input to the loop filter 23 during the CR field 301 of the preamble field shown in FIG. 4 and, when the BTR field 302 begins, digital signals having a bit pattern of binary (0101 . . . 01) will be made the input to the loop filter 23. As a result, when the BTR field 302 begins, the output of the loop filter 23 takes on a prescribed value of a low level, so that the CR operation is prevented from being affected by the failure to recover the optimal timing at the beginning of the BTR field 302.
The foregoing configuration is described in, for example, the Japanese Patent Disclosure Gazette No. 1990-1675. The U.S. Pat. No. 4,871,975 also refers to a carrier recovery circuit for offset QPSK demodulators.
In this configuration, during the BTR field, the carrier can be stably recovered, without being affected by sample timing, by projecting the vector of received signals on one axis of the phase plane and using the amplitude of that projected vector as input to the loop filter.
The CR circuit described above, however, involves the problem that the Costas loop controls in the BTR field is not accomplished on the basis of an accurately determined phase error of the carrier but on the basis of a phase difference approximated by using the difference of the projected vector. Moreover, as the input to the loop filter oscillates symbol by symbol, the control voltage for the VCO supplied from the loop filter is accompanied by jitter, which prevents the band of the loop filter from being widened under low C/N ratio condition.